Modern-day electronics require multiple patterned layers of electrically or optically active materials, sometimes over a relatively large substrate. Electronics such as radio frequency identification (RFID) tags, photovoltaics, optical and chemical sensors all require some level of patterning in their electronic circuitry. Flat panel displays, such as liquid crystal displays or electroluminescent displays (for example, OLED), rely upon accurately patterned sequential layers to form thin film components of the backplane. These components include capacitors, transistors, and power buses. The industry is continually looking for new methods of materials deposition and layer patterning for both performance gains and cost reductions. Thin film transistors (TFTs) may be viewed as representative of the electronic and manufacturing issues for many thin film components. TFTs are widely used as switching elements in electronics, for example, in active-matrix liquid-crystal displays, smart cards, and a variety of other electronic devices and components thereof.
There is a growing interest in depositing thin film semiconductors on plastic or flexible substrates, particularly because these supports are more mechanically robust, lighter weight, and allow more economical manufacturing, for example, by allowing roll-to-roll processing. Plastics, however, typically limit device processing to below 200° C. There are other many issues associated with plastic supports when using traditional photolithography during conventional manufacturing, making it difficult to perform alignments of transistor components across typical substrate widths up to one meter or more. Traditional photolithographic processes and equipment may be seriously impacted by the substrate's maximum process temperature, solvent resistance, dimensional stability, water, and solvent swelling, all key parameters in which plastic supports are typically inferior to glass.
The discovery of practical inorganic semiconductors as a replacement for current silicon-based technologies has also been the subject of considerable research efforts. For example, metal oxide semiconductors are known that constitute zinc oxide, indium oxide, gallium indium zinc oxide, tin oxide, or cadmium oxide deposited with or without additional doping elements including metals such as aluminum. Such semiconductor materials, which are transparent, can have additional advantages for certain applications. Additionally, metal oxide dielectrics such as alumina (Al2O3) and TiO2 are useful in practical electronics applications as well as optical applications such as interference filters. Dielectric materials that are easily processable and patternable are also important to the success of low cost and flexible electronic devices. In addition, metal oxide materials can serve as barrier or encapsulation elements in various electronic devices. These materials also require patterning so that a connection can be made to the encapsulated devices.
Atomic layer deposition (ALD) can be used as a fabrication step for forming a number of types of thin-film electronic devices, including semiconductor devices and supporting electronic components such as resistors and capacitors, insulators, bus lines, and other conductive structures. ALD is particularly suited for forming thin layers of metal oxides in the components of electronic devices. General classes of functional materials that can be deposited with ALD include conductors, dielectrics or insulators, and semiconductors. A number of device structures can be made with the functional layers described above.
There is growing interest in combining ALD with a technology known as selective area deposition (SAD). As the name implies, selective area deposition involves treating portion(s) of a substrate such that a material is deposited only in those areas that are desired, or selected. The majority of SAD work to date has focused on the problem of patterning a single material during deposition. There persists a problem of combining multiple SAD steps to form working devices, Processes for building complete devices need to be able to control the properties the critical interfaces, particularly in field effect devices like TFTs.
The majority of electronic devices require a high quality dielectric layer. Although there are many approaches to forming a high quality dielectric layer, they typically fall into one of two categories: a single thick layer of a single material or multiple layers of differing material types. In the case of devices which use a single layer dielectric, large thicknesses are required for defect mitigation to ensure high device yield. This required layer thickness typically requires long processing times and limits the functionality of field effect devices. Devices formed with a multilayer stack of materials use thin layers of materials deposited using the same equipment requiring complex equipment design and multiple precursors. Accordingly, there still remains a need for a high quality dielectric that can be formed from a single material for ease of processing and single precursors, and that doesn't require a thick layer for performance and device yield. Additionally, a method is needed to simply pattern this layer for easy device integration.
A particularly useful electronic device in building functional circuitry is an inverter, which functions to invert the polarity of an input signal. In CMOS circuitry, inverters are typically easy to design but disadvantageously expensive to produce and utilize complicated production processes. It is possible to build all NMOS or PMOS inverters, however particularly for enhancement-depletion mode circuits there are challenges to independently controlling the behavior of each transistor in the inverter circuit. Typically, the depletion mode transistor will have a thicker semiconductor layer than the enhancement mode transistor, increasing process complexity and increasing cost. Other alternatives include using dual gate architectures or multilayer semiconductor stacks, which have similar issues of process complexity and cost. As the industry endeavors to build circuitry using printing methods, individual transistor size has a direct impact on the overall circuit footprint on something like a label, as the individual component transistors are sized using their channel dimensions. There remains a need to build high quality inverters using simple processes, by employing novel architectures to control transistor, and therefore, circuit performance.